Overview
Implementation of the MCP4EDA framework providing Electronic Design Automation (EDA) tool integration for AI assistants such as Claude Desktop and Cursor IDE. This MCP server exposes a unified interface to perform Verilog synthesis with Yosys, simulate designs with Icarus Verilog, and run complete ASIC design flows using OpenLane (Dockerized) while enabling waveform and layout inspection via GTKWave and KLayout. It supports viewing final GDSII layouts, reading OpenLane reports for PPA metrics, and producing intermediate artifacts (netlists, DEF files, etc.). The system is designed to run locally, requiring a local EDA toolchain installation and optional Docker Desktop, with Docker MCP integration to streamline interactions with the Claude/Cursor clients. The repository includes setup instructions for installation, project structure, and usage examples for synthesis, simulation, ASIC flows, and waveform analysis. It emphasizes troubleshooting and debugging guidance for tool installation, path configuration, and GUI launching issues. OpenLane timeouts and GUI accessibility considerations are documented to aid reliable operation in diverse environments.
Features
Verilog Synthesis
Synthesize Verilog code using Yosys for various FPGA targets (generic, ice40, Xilinx).
Verilog Simulation
Simulate designs using Icarus Verilog with automated testbench execution.
Waveform Viewing
Launch GTKWave for VCD file visualization and signal analysis.
ASIC Design Flow
Complete RTL-to-GDSII flow using OpenLane with Docker integration.
Layout Viewing
Open GDSII files in KLayout for physical design inspection.
Report Analysis
Read and analyze OpenLane reports for PPA metrics and design quality assessment.
Who Is This For?
- AI assistants:Enable AI assistants to perform Verilog synthesis, simulation, and design flows locally.
